By Nathan Vifflin
AMSTERDAM (Reuters) -The CEO of imec, one of the world’s top semiconductor R&D firms, has said the industry needs to steer towards reconfigurable chip architectures if it wants to avoid becoming a bottleneck for the future generations of artificial intelligence.
Rapid AI algorithm innovation outpaces the current strategy of developing specific, raw-power-focused chips, leading to major drawbacks in energy, cost and hardware development speed, CEO Luc Van den hove said in a statement seen by Reuters ahead of its publication.
“There is a huge inherent risk of stranded assets because by the time the AI hardware is finally ready, the fast-moving AI software community may have taken a different turn,” he said.
Some, like OpenAI, have taken the path of building custom chips to speed up innovation, a move Van den hove said was risky and uneconomical for most.
The Interuniversity Microelectronics Centre (imec) pioneers many semiconductor breakthroughs that chipmakers like TSMC and Intel often widely adopt years down the line.
As the AI industry moves beyond large language models to agentic AI and physical AI for medical or autonomous driving applications, Van den hove sees future chips regrouping all necessary capabilities into building blocks called supercells.
“A network-on-chip will steer and reconfigure these supercells so they can be quickly adapted to the latest algorithm requirements,” Van den hove said.
This will require true three dimensional stacking, a manufacturing technique where layers of logic and memory silicon are bonded together, he added.
Belgium-based imec was a significant contributor to the advancement and refinement of 3D stacking, a technology that will be featured in TSMC’s A14 and Intel’s 18A-PT future nodes.
The research and development firm will hold its flagship conference, ITF World, on Tuesday and Wednesday in Antwerp, Belgium.
(Reporting by Nathan Vifflin in Amsterdam, editing by Milla Nissi-Prussak)
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